1. Field of the Invention
The present invention relates to planarization after forming an inter-layer insulating film and an arrangement of a diffusion area in drain and a diffusion area in source formed by a layer in which impurities are diffused in a non-volatile semiconductor memory device and a method for producing the same.
2. Discussion of Background
An AND-type flash memory is one type of a large-capacity non-volatile flash memory in a semiconductor memory devices. The AND-type flash memory is described, for example, in IEDM *92 Technical Digest P. 991-993, *A 1.28 xcexcm2 contactless memory cell technology for a 3 V-only 64 M bit EEPROM*, H. Kume et al.).
FIG. 13 is an equivalent circuit diagram of a region of memory cell array of a conventional AND-type flash memory and a connecting region for connecting the region of memory cell array to a region of peripheral circuit (not shown) described in the above document. In FIG. 13, numerical reference 1 designates a memory cell comprises a single transistor. Numerical reference 2 designates a floating gate of the transistor comprising the memory cell 1, which floating gate is composed of a plurality of conductive layers as described below. Numerical reference 3 designates a control gate; numerical references 4 and 5 respectively designate a local data line and a local source line, both of which are mode of an N+ diffusion layer; numerical reference 6 designates a grovel data line made of a metallic wire; numerical reference 7 designates a common source line which is connected to ground potential; numerical reference 8 designates a first selection transistor for connecting the grovel data line 6 to the local data line 4; numerical reference 9 designates a second selection transistor for connecting the local source line 5 to the common source line 7; numerical reference 10 designates a word line which is arranged at a substantially right angle with respect to the local data line and connected to the control gate 3; numerical reference 11 designates a region of memory cell array in which the memory cells 1 are arranged in a matrix-like form; numerical reference 12 designates a region of first selection gate in which the first selection transistors 8 are arranged; and numerical reference 13 designates a region of second selection gate in which the second selection transistors 9 are arranged, wherein the region of first selection gate 12 and the region of second selection gate 13 are connecting regions adjacent to the region of memory cell array 11 and the region of peripheral circuit (not shown).
In the next, operation of the conventional AND-type flash memory described above will be briefly explained. The operation to be described below is recently improved and is different from the operation described in the above document. There are three types of operation of (a) write, (b) read, and (c) erase. A characteristic of the operation in the above AND-type flash memory is that all memory cells connected to a word line simultaneously become any one of operational conditions among the above three types.
In FIGS. 14a through 14c, a memory cell array in a matrix-like form of 2xc3x972 is shown for explaining the operation. A case that a memory cells c1 and c2 are selected will be described, where a condition that electrons are injected into a floating gate is expressed by data of xe2x80x9c1xe2x80x9d, and a condition that electrons are not injected is expressed by data of xe2x80x9c0xe2x80x9d.
(a) Write Operation
In write operation, xe2x80x9c1xe2x80x9d is written in the memory cell c1 and xe2x80x9c0xe2x80x9d is written in the memory cell c2. As shown in FIG. 14a, electric potential of a word line w1 to be selected is 18 V; electric potential of a non-selecting word line w2 is 4.5 V; electric potential of a local data line d1 connected to the memory cell c1 is 0 V; electric potential of a local data line connected to the memory cell c2 is 6.5 V; local source lines s1, s2 are in an opened state, (i.e. floating); and electric potential of a substrate is 0 V. Under such a condition, because a potential difference between the word line w1 and the local data line d1 is large, xe2x80x9c1xe2x80x9d is written in only the floating gate of memory cell c1 by injecting electrons thereinto.
(b) Read Operation
In read operation, data written in the write operation, namely xe2x80x9c1xe2x80x9d from the memory cell c1 and xe2x80x9c0xe2x80x9d from the memory cell c2, are read out. As shown in FIG. 14b, electric potential of the word line to be selected w1 is 5 V; electric potential of the non-selecting word line w2 is 0 V; electric potential of local data lines d1, d2 is 1 V; electric potential of local source lines s1, s2 is 0 V; and electric potential of the substrate is 0 V. Under such a condition, because electrons are injected into a floating gate of memory cell c1, Vth is high and therefore an electric current does not flow into the local data line d1, a transistor of the memory cell c1, and the local source line s1. On the contrary, because electrons are not implanted into a floating gate of memory cell c2, Vth is low and therefore an electric current flows into the local data line d2, a transistor of the memory cell c2, and the local source line s2.
(c) Erase Operation
In erase operation, a word xe2x80x9cerasexe2x80x9d means that all of the data written in the write operation are changed to xe2x80x9c0xe2x80x9d. As shown in FIG. 14c, electric potential of the word line w1 to be selected is xe2x88x9218 V; electric potential of the non-selecting word line w2 is 0 V; electric potential of the local data lines d1, d2 is 0 V; the local source lines s1, s2 are in an opened state; and electric potential of the substrate is 0 V. Accordingly, electrons are drawn out from the floating gate of memory cell c1 and thereby the memory cells c1 and c2 have data of xe2x80x9c0xe2x80x9d.
In the next, layout pattern after forming a first metallic film (i.e. first metal) is shown in FIG. 15, which corresponds to the region of memory cell array 11 and the region of first selection gate 12 in FIG. 13. Hereinbelow, portions of the layout pattern of FIG. 15 are explained in correspondence with circuit components of the equivalent circuit diagram of FIG. 13. The floating gate 2 shown in FIG. 13 is composed of two layers of polysilicon. Although amorphous silicon can substitutes for polysilicon, a case that polysilicon is used will be described hereinbelow. Numerical reference 21 of FIG. 15 designates a lower floating gate made of first polysilicon; and numerical reference 22 designates an upper floating gate made of second polysilicon. Numerical reference 23 of FIG. 15 designates third polysilicon for composing the control gate 3 and the word line 10 of FIG. 13, wherein although the third polysilicon may be substituted by a double-layer structure of polysilicon and silicide for reducing resistance, a case that polysilicon is used will be described hereinbelow. Numerical reference 24 of FIG. 15 designates a diffused area in drain of the transistors of the memory cell, which area is made of an N+ diffusion layer. Hereinbelow, this diffused area in drain is referred to as a drain area. The drain area corresponds to the local data line 4 of FIG. 13. Numerical reference 25 of FIG. 15 is a diffused area in source of the transistors of the memory cell, which area is made of an N+ diffusion layer. Hereinbelow, the diffused area in source is referred to as a source area. The source area corresponds to the local source line 5 of FIG. 13. Numerical reference 26 of FIG. 15 corresponds to the grovel data line 6 of FIG. 13 made of a first metal; numerical reference 27 designates a drain source area of the first selection transistor 8; numerical reference 28 designates a gate of the first selection transistor 8 made of the third polysilicon; numerical reference 29 designates a metal contact for connecting the grovel data line 26 to the drain source area 27 of the first selection transistor; and numeral reference 30 designates trench isolation formed as an isolating area.
Further, numerical references 31 through 33 of FIG. 15 respectively designate remaining gates of the first polysilicon through the third polysilicon formed in the region of first selection gate 12, which gates are provided to leave patterns of polysilicon used for the gates of memory cell transistors to other than the region of memory cell array.
A boundary k between the region of memory cell array and the region of first selection gate 12 as a connection region thereto shown in FIG. 15 is at an end portion of the region of memory cell array, namely an edge of the memory cell. However, the drain area 24 and the source area 25 of the transistors of memory cell continuously extend from the region of memory cell array 11 to the region of first selection gate 12. Therefore, the drain area 24 and the source area 25 will be designated by the same references even in the region of first selection gate 12. The drain area 24 and the source area 25 of the transistors of memory cell extend on the memory cell array 11 substantially in parallel and substantially in linear. Further, the drain area 24 of the transistors of memory cell is connected to the drain source area 27 of the first selection transistor at the region of first selection gate 12.
In the next, FIG. 16 shows cross sectional views of the above-described regions. FIG. 16a is a cross sectional view of the region of memory cell array 11 in FIG. 15 taken along a line Ixe2x80x94I; FIG. 16b is a cross sectional view of the region of first selection gate 12 shown in FIG. 15 taken along a line IIxe2x80x94II; and FIG. 16c is a cross sectional view of a generally used region of region of peripheral circuit (not shown) of AND-type flash memory.
In FIG. 16a, numerical reference 40 designates a silicon substrate; numerical reference 41 designates a tunnel insulation film; numerical reference 42 designates an inter-layer insulating film as an insulating layer; numerical reference 43 designate an oxide/nitride/oxide multi-layered dieelectric (hereinbelow referred to as ONO film) which is a multi-layered insulating film composed of a silicon oxide film, a silicon nitride film, and silicon oxide film; and numerical reference 44 designates an inter-layer insulating film located below the first metal.
As for FIG. 16b, explanation of the numerical references is omitted because these are the same as those shown in FIG. 15 and FIG. 16a. A primary feature in FIG. 16b is that the remaining gate 31 of the first polysilicon is continuously connected to the remaining gate 32 of the second polysilicon.
In FIG. 16c, numerical reference 45 designates a gate insulating film of transistor in the peripheral circuit; numerical reference 46 designates a gate of transistor made of the third polysilicon; numerical reference 47 designates a drain source area of transistor; numerical reference 48 designates a metal contact; and numerical reference 49 designates a first metal wire.
Then a method of producing the above-mentioned conventional AND-type flash memory will be described. FIG. 17 is a schematic flow chart of the method of producing, and FIGS. 18a through 26c show cross sectional views of the regions respectively by manufacturing steps. FIGS. 18a, 19a, 20a, 21a, 22a, 23a, 24a, 25a, and 26a show the region of memory cell array; FIGS. 18b, 19b, 20b, 21b, 22b, 23b, 24b, 25b, and 26b show the region of first selection gate; and FIGS. 18c, 19c, 20c, 21c, 22c, 23c, 24c, 25c, and 26c show the region of generally used peripheral circuit in an AND-type flash memory, respectively showing in section like FIGS. 16a, 16b, and 16c. 
In the next, the manufacturing steps will be explained in correspondence with the cross sectional views of these regions in a sequential manner, based on FIG. 17.
(1) a first step (formation of the isolating area): FIGS. 18a through 18c correspond thereto. The trench isolation 30 is formed as isolation in the silicon substrate 40.
(2) a second step (formation of the tunnel insulation film): FIGS. 19a through 19c correspond thereto. The tunnel insulation film 41 having a thickness of about 8 through 15 nm is formed between the silicon substrate 40 and the lower floating gate 21 to be formed in a post process.
(3) a third step (formation of the lower floating gate): FIGS. 20a through 20c correspond thereto. Numerical reference 51 designates first polysilicon of the region of peripheral circuit to be removed in a post process; and numerical reference 52 designates a silicon nitride film. The first polysilicon having a thickness of about 80 through 120 nm and the silicon nitride film having a thickness of about 180 through 250 nm are deposited, and the lower floating gate 21 and the remaining gate 31 of the first polysilicon are formed.
(4) a fourth step (formation of the first drain source area): FIGS. 21a through 21c correspond thereto. The drain area 24 and the source area 25 are formed in a part of the region of memory cell array and a part of the connecting region by implanting ions.
(5) a fifth step (formation of the inter-layer insulating film and planarization): FIGS. 22a through 22c correspond thereto. After laminating the inter-layer insulating film having a thickness of about 500 through 800 nm, the inter-layer insulating film in the region of peripheral circuit is completely removed by planarization, whereby the inter-layer insulating film 42 is left in the region of memory cell array and the connecting region.
(6) a sixth step (removal of the silicon nitride film): FIGS. 23a through 23c correspond thereto. The silicon nitride film 52 is removed.
(7) a seventh step (formation of the upper floating gate): FIGS. 24a through 24c correspond thereto. Numerical reference 53 designates second polysilicon in the region of peripheral circuit to be removed in a post step. The second polysilicon having a thickness of about 30 through 80 nm is deposited, and the upper floating gate 22 and the remaining gate 32 of the second polysilicon are formed.
(8) an eighth step (formation of the ONO film): FIGS. 25a through 25c correspond thereto. The ONO film 43 having a thickness of about 10 through 20 nm in a conversion value as an oxide film, which will be an inter-layer insulating film between the upper floating gate 22 and the control gate 23 to be form in a post step, is formed. Succeedingly, the tunnel insulating film of the region of peripheral circuit, the first polysilicon, the second polysilicon, and the ONO film are removed.
(9) a ninth step (formation of the gate insulating film): FIGS. 26a through 26c correspond thereto. The gate insulating film 45 of transistor in the peripheral circuit is formed.
(10) a tenth step (formation of the control gate and the gate of transistors in the region of peripheral circuit and that in the connecting region): FIGS. 27a through 27c correspond thereto. The third polysilicon having a thickness of about 100 though 300 nm is deposited and the control gate 23 of the region of memory cell array, the remaining gate 33 of the third polysilicon in the connecting region, the gate 28 of the first selection transistor (shown in FIG. 15 not in FIG. 27b), and gate 46 of transistor in the peripheral circuit are formed.
(11) an eleventh step (formation of the second drain source area): FIGS. 28a through 28c correspond thereto. The drain source area 47 in the region of peripheral circuit and the drain source area 27 of the connecting region (shown in FIG. 15 not in FIG. 28b) are formed by implanting ions.
(12) a twelfth step (formation of the inter-layer insulating film under the first metal, formation of the metal contact and formation of the first metal): FIGS. 16a through 16c correspond thereto. After forming the inter-layer insulating film 44, the metal contact 48 and the metal contact 29 (shown in FIG. 15 not in FIG. 16b) are respectively formed in the region of peripheral circuit and in the connecting region. Thereafter, metal wires of the grovel data line 26 in the region of memory cell array and the connecting region and those in the region of peripheral circuit 49 are formed.
The method of producing has been wholely described in the above. Further, the fifth step of the formation of the inter-layer insulating film and the planarization will be described in detail because this has been improved recently. In FIGS. 28a through 28c and 29a through 29c, cross sectional views of the regions are shown as in the above. In FIGS. 29a through 29c, after depositing the inter-layer insulating film 42, chemical mechanical polish (hereinbelow referred to as CMP) is conducted and further etch back is conducted by dry etching to thereby substantially remove the inter-layer insulating film in the region of peripheral circuit-However, as shown in FIG. 29c, small pieces of remaining inter-layer insulating film 54 exists in the silicon nitride film 52 of the region of peripheral circuit, wherein the remaining inter-layer insulating film works as a mask for the silicon nitride film in the post step of removing the silicon nitride film to thereby cause a problem of remaining first polysilicon. Accordingly, as shown in FIGS. 30a through 30c, wet etching is additionally performed to thereby remove the remaining inter-layer insulating film 54 in the region of peripheral circuit almost completely.
However, in the above described semiconductor device and the method of producing the device, there were three problems as below.
The first problem is that a seam 55 occurred in the inter-layer insulating film 42 within the region of first selection gate as the connecting region as shown in FIG. 30b. 
In FIG. 31, a layout pattern after the wet etching is performed to the region of memory cell array 11 and the region of first selection gate 12 in correspondence with FIG. 15 is shown. Numerical reference 56 designates a laminating pattern of the first polysilicon and the silicon nitride film. Although a seam was not generated in the region of memory cell array designated by reference A in FIGS. 15 and 31 having a wide clicking width by the laminating pattern 56, a seam 55 was produced in a portion where a clicking width is narrow designated by reference B in FIGS. 15 and 31 within the connecting region. A reason for producing this is considered that portions having a narrow clicking width by the laminating pattern 56 had a tendency that a characteristic of burying was bad despite the formation of the inter-layer insulating film by chemical vapor deposition (hereinbelow, referred to as CVD). Accordingly, it is considered that when wet etching is conducted for removing the remaining inter-layer insulating film, in the portions having a narrow clicking width are excessively etched to thereby produce a seam 55.
If such a seam exists, when the remaining gate 32 of the second polysilicon is formed in a post step, the remaining gate 32 of the second polysilicon is shorted to the drain area 24 of transistor of the memory cell. Ordinarily, the remaining gate 32 of the second polysilicon is applied with constant electric potential. Therefore, there was a problem that electric potential of the local data line 4, namely that of the drain area of memory cell transistor, became abnormal and normal operation could not be conducted.
Further, although it was possible to prevent a seam caused by wet etching from generating by covering the region of first selection gate 12 with a resist, there was another problem that the method of producing was complicated because the number of masks was increased.
In the next, the second problem was that the drain area 24 of memory cell transistor within the region of first selection gate 12 was difficult to be formed by shadowing. In other words, although the first drain source was formed after forming the first polysilicon and the silicon nitride film, when the drain source was formed by obliquely implanting ions as shown in FIG. 33, the ions were difficult to be implanted to a place to be the drain area 24 of memory cell transistor in the region of first selection gate 12 having a narrow interval of the first polysilicon, not like in the region of memory cell array 11. This is because the pattern of the first polysilicon 31 and of the silicon nitride film 52 works as a barrier, whereby the drain area 24 of memory cell transistor can not be sufficiently formed.
Heretofore, the region of memory cell array 11 and the region of first selection gate 12 are exemplified. However, this problem also occurs in the region of second selection gate 13 which is a connecting region, which is similar to the region of first selection gate 12.
FIG. 34 shows a positional relationship between the region of memory cell array 11, the drain area 24 of memory cell transistor within the region of first selection gate 12, and the source area 25 of memory cell transistor within the region of second selection gate 13. From this Figure, it is known that the drain area 24 of memory cell transistor and the source area 25 of memory cell transistor respectively extend from the region of memory cell array 11. Therefore, also in the region of second selection gate 13, the above-mentioned problem occurred in this extending area.
The third problem is about an yield of device caused by the region of memory cell array. As shown in FIG. 15, the drain area 24 and the source area 25 of memory cell transistors are adjacent to each other interposing the trench isolation 30. When the drain area 24 was shorted to the source area 25 in the memory cell transistors by a pattern defect such as a foreign matter generated in the above trench isolation 30, the drain area 24 of memory cell transistor, namely the local data line 4, and the source area 25, namely the local source line 5, were applied with different values of electric potential as described in correspondence with FIGS. 14a through 14c, whereby the memory cell connected to the local data line and/or the local source line could not be normally operated. Accordingly, a part of the memory cell in such a portion can not be used to thereby cause a drop of yield.
It is an object of the present invention to solve the above-mentioned problems inherent in the conventional techniques and to restrict production of seams in a connecting region.
Another object of the present invention is to prevent short from occurring even though seams are generated.
Another object of the present invention is to suppress occurrence of shadowing when the drain source are implanted.
Another object of the present invention is to restrict a drop of yield caused by short between a local data line and a local source line.
Another object of the present invention is to provide a method of producing a semiconductor device by which production of seams is restricted without increasing the number of masks and to suppress occurrence of shadowing.
According to a first aspect of the present invention, there is provided a non-volatile semiconductor memory device comprising:
a semiconductor substrate,
memory cells,
a region of memory cell array in which the memory cells are arranged in a matrix-like form,
a region of peripheral circuit,
a connecting region for connecting the region of memory cell array to the region of peripheral circuit, and
conductive layers provided in the substrate with intervals between each other, wherein
the interval of the conductive layers in the region of memory cell array is substantially equal to the interval in the connecting region.
According to a second aspect of the present invention, there is provided a non-volatile semiconductor memory device according to the first aspect of the invention, wherein
the intervals are 0.5 xcexcm or more.
According to a third aspect of the present invention, there is provided a non-volatile semiconductor memory device comprising:
a semiconductor substrate,
memory cells formed in the semiconductor substrate,
transistors for constituting the memory cells,
diffused areas in drain and diffused area in source both for constituting the transistors, and
a region of memory cell array in which the memory cells are arranged in a matrix-like form, wherein
the diffused areas in drain and the diffused areas in source extend in a predetermined direction and substantially in parallel to each other on the region of memory cell array; and
the diffused areas in drain and the diffused areas in source are respectively formed interposing isolating areas.
According to a fourth aspect of the present invention, there is provided a non-volatile semiconductor memory device according to the third aspect of the invention, further comprising:
a region of peripheral circuit,
a connecting region for connecting the region of memory cell array to the peripheral circuit,
conductive layers provided in the substrate with intervals between each other, wherein
between the conductive layers, the diffused areas in drain or the diffused areas in source are respectively provided; and
the interval in the the region of memory cell array is substantially equal to the interval in the connecting region and the connecting region.
According to a fifth aspect of the present invention, there is provided a non-volatile semiconductor memory device according to the fourth aspect of the invention, wherein
the intervals are 0.5 xcexcm or more
According to a sixth aspect of the present invention, there is provided a method of producing a non-volatile semiconductor memory device having memory cells, a region of memory cell array in which the memory cells are arranged in a matrix-like form, a region of peripheral circuit, and a connecting region for connecting the region of memory cell array to the region of peripheral circuit, which comprises:
a step of forming conductive layers in the region of memory cell array, in the region of peripheral circuit, and in the connecting region,
a step of patterning the conductive layers so that the interval between the conductive layers in the region of memory cell array is substantially equal to the interval in the connecting region,
a step of forming insulating layers on the conductive layers, and
a step of substantially planarizing the insulating layers
According to a seventh aspect of the present invention, there is provided a method of producing non-volatile semiconductor memory device according to the sixth aspect of the invention, wherein
the intervals of conductive layers is 0.5 xcexcm or more.
According to an eighth aspect of the invention, there is provided a non-volatile semiconductor memory device comprising:
a semiconductor substrate,
memory cells formed in the semiconductor substrate,
transistors for constituting the memory cells,
diffused areas in drain and diffused in source both for constituting the transistors,
a region of memory cell array in which the memory cells are arranged in a matrix-like form, wherein
the diffused areas in drain and the diffused areas in source extend in a predetermined direction and substantially in parallel to each other on the region of memory cell array; and
the diffused areas in drain are formed interposing isolating areas.
According to a ninth aspect of the present invention, there is provided a non-volatile semiconductor memory device according to the eighth aspect of the invention, wherein
adjacent memory cells among the memory cells commonly have the diffused area in source; and
the width of the diffused areas in drain and the width of the diffused areas in source are substantially equal to each other.